The present invention disclosed herein relates to memory devices, and more particularly, to non-volatile memory devices.
A non-volatile memory device retains its stored information even when there is no power supply. A flash memory device as a representative non-volatile memory device stores information based on whether electric charges are stored or not in a floating gate interposed between a control gate and a substrate.
FIG. 1 is a cross sectional view of a conventional non-volatile memory device.
Referring to FIG. 1, a device isolation layer 12 is formed in a semiconductor substrate 10 to define an active region and a tunnel insulation layer 14 is formed on the active region in a non-volatile memory device such as a flash memory device. A floating gate 16 is formed on the tunnel insulation layer 14 and a blocking insulation pattern 18 is formed on the floating gate 16 and the device isolation layer 12. A control gate electrode 20 is formed on the blocking insulation pattern 18. In a typical non-volatile memory device, the floating gate 16 is formed protruding higher than the device isolation layer 12 in order to argument a coupling ratio by increasing a surface area of the floating gate 16 that contacts the blocking insulation pattern 18. A typical structure of this non-volatile memory device may have various limitations if an interval between the floating gates 16 is decreased due to the high degree of integration. If the height of the floating gate 16 is increased and the interval between the floating gates 16 is decreased, a conductive layer for forming the control gate electrode 20 may not be completely filled between the floating gates 16. Additionally, as illustrated in FIG. 1, a parasitic capacitance C1 may be formed between the floating gates 16, and as the interval between the floating gates 16 is reduced, the parasitic capacitance may increase. Therefore, an interference phenomenon between adjacent memory cells may be significant. Additionally, if a high-k dielectric layer is used as the blocking insulation pattern 18 between the charge storage pattern 16 and the control gate electrode 20 to increase the coupling ratio, a leakage current Ileakage may increase between the charge storage pattern 16 and the control gate electrode 20.
In a case of an erase operation of a non-volatile flash memory including a doped silicon/oxide/nitride/oxide/silicon (SONOS) structure and a floating gate, because a back tunneling current flows, a speed of the erase operation may deteriorate.